A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier(Electronic Circuits)

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概要

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• A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation Implemented in a standard 0.25 μm CMOS technology, the SHA achieves 80 dB spurious-free dynaniic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm^2 and dissipates 33 mW from a single 2.5 V supply.

• 社団法人電子情報通信学会の論文
• 2003-10-01

著者

• Hsu Cheng-chung

  Department Of Electronics Engineering National Chiao-tung University

• Hsu Cheng-chung

  Department Of Electrical Engineering National Taiwan University

• WU Jieh-Tsorng

  Department of Electronics Engineering, National Chiao-Tung University

• Wu Jieh-tsorng

  Department Of Electronics Engineering National Chiao-tung University

関連論文

• A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier(Electronic Circuits)
• A Novel Delta-Sigma Time-to-Digital Converter Using Delay Line
• Structural Generation of Current-Mode Filters Using Tunable Multiple-Output OTAs and Grounded Capacitors

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