A Novel Delta-Sigma Time-to-Digital Converter Using Delay Line
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概要
- 論文の詳細を見る
- 1999-05-05
著者
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WU Jieh-Tsorng
Department of Electronics Engineering, National Chiao-Tung University
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Wu Jieh-tsorng
Department Of Electronics Engineering National Chiao-tung University
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WANG Hsi-Yuan
Department of Electronics Engineering, National Chiao-Tung University
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Wang Hsi-yuan
Department Of Electronics Engineering National Chiao-tung University
関連論文
- A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier(Electronic Circuits)
- A Novel Delta-Sigma Time-to-Digital Converter Using Delay Line