Design of a 4×4 Banyan Network Switch with a Dual-Buffer Structure Using SFQ Logic Circuits(Special Issue on Superconductor Digital/Analog Circuit Technologies)

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概要

• 論文の詳細を見る

• We have designed a 4×4 Banyan switch using SFQ logic circuits. The switch is composed of three parts; one is an input buffer, the second is a contention solver which checks packet contention in a distribution network, and the third is a packet distribution network which distributes contention-free packets to their destination address. The packet distribution network is composed of Batcher-Banyan switch with the input buffer. The contention solver decides to send a data packet to the distribution network, using only internal routing tags which are added to packets in the switch. As the circuit is composed of two parts, the contention solver and the packet distribution network, the transfer rate is raised because it doesn't need to wait any more while a data packet passes through the distribution network. Simulation results using JSIM show that the switch circuit can operate at a clock frequency of 40 GHz.

• 社団法人電子情報通信学会の論文
• 2003-01-01

著者

• Myoren Hiroaki

  Faculty Of Engineering Saitama University

• Takada Susumu

  Faculty Of Engineering Saitama University

• TAKAHASHI Junji

  Faculty of Engineering, Saitama University

• Takahashi Junji

  Faculty Of Engineering Saitama University

関連論文

• Design of a 4×4 Banyan Network Switch with a Dual-Buffer Structure Using SFQ Logic Circuits(Special Issue on Superconductor Digital/Analog Circuit Technologies)
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