A Low-Power Branch Predictor for Embedded Processors(Computer Systems)

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概要

• 論文の詳細を見る

• Even in embedded processors, the accuracy in a branch prediction significantly affects the performance. In designing a branch predictor, in addition to accuracy, microarchitects should consider area, delay and power consumption. We propose two techniques to reduce the power consumption; these techniques do not requires any additional storage arrays, do not incur additional delay (except just one MUX delay) and never deteriorate accuracy. One is to look up two predictions at a time by increasing the width (decreasing the depth) of the PHT (Prediction History Table). The other is to reduce unnecessary accesses to the BTB (Branch Target Buffer) by accessing the PHT in advance. Analysis results with Samsung Memory Compiler show that the proposed techniques reduce the power consumption of the branch predictor by 15-52%.

• 社団法人電子情報通信学会の論文
• 2004-09-01

著者

• Park Sung

  Processor Architecture Lab. Samsung Electronics

• Chung S

  Samsung Electronics

• Park Gi

  Processor Architecture Lab. Samsung Electronics

• CHUNG Sung

  Processor Architecture Lab, Samsung Electronics Co.

関連論文

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