A Low-Power Tournament Branch Predictor(Computer Systems)

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概要

• 論文の詳細を見る

• This letter proposes a low-power tournament branch predictor, in which the number of accesses to the branch predictors (local predictor or global predictor) is reduced. Analysis results with Samsung Memory Compiler show that the proposed branch predictor reduces the power consumption by 24-45%, compared to the conventional tournament branch predictor, not requiring any additional storage arrays, not incurring any additional delay and never harming accuracy.

• 社団法人電子情報通信学会の論文
• 2004-07-01

著者

• Park Sung

  Processor Architecture Lab. Samsung Electronics

• Chung S

  Samsung Electronics

• Park Gi

  Processor Architecture Lab. Samsung Electronics

• CHUNG Sung

  Processor Architecture Lab, Samsung Electronics Co.

関連論文

• Utilization of the On-Chip L2 Cache Area in CC-NUMA Multiprocessors for Applications with a Small Working Set(Networking and System Architectures)(Hardware/Software Support for High Performance Scientific and Engineering Computing)
• A Low-Power Branch Predictor for Embedded Processors(Computer Systems)
• A Low-Power Tournament Branch Predictor(Computer Systems)

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