Algorithms for Matrix Multiplication and the FFT on a Processor Array with Separable Buses(Regular Section)
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概要
- 論文の詳細を見る
This letter presents parallel algorithms for matrix multiplication and the fast Fourier transform (FFT) that are significant problems arising in engineering and scientific applications. The proposed algorithms are designed on a 3-dimensional processor array with separable buses (PAS_b). We show that a PAS_b consisting of √N×√N×h processors can compute matrix multiplication of size √N×√N and the FFT of size N in O(√N/h+logN) time, respectively. In order to examine ease of hardware implementation, we also evaluate the VLSI complexity of the algorithms. A result obtained achieves an optimal bound on area-time complexity when h=O(√N/logN).
- 社団法人電子情報通信学会の論文
- 2003-01-01
著者
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TATSUMI Shoji
Faculty of Engineering, Osaka City University
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Tatsumi Shoji
Faculty Of Engineering Osaka City University
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Abe Ken'ichi
Graduate School Of Engineering Tohoku University
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Tatsumi S
Osaka City Univ. Osaka‐shi Jpn
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Maeba Takashi
Department Of Information Systems Engineering Kobe University Of Mercantile Marine
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SUGAYA Mitsuyoshi
NRI Secure Technologies, Ltd.
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Sugaya Mitsuyoshi
Nri Secure Technologies Ltd.
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