CMOS Zero-Temperature-Coefficient Point Voltage Reference with Variable-Output-Voltage Level(<Special Section>Analog Circuit Techniques and Related Topics)
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概要
- 論文の詳細を見る
A CMOS voltage reference circuit based on a voltage at the zero-temperature-coefficient point of drain current is proposed. The output voltage of the proposed circuit is variable by a substrate bias. The proposed circuit is simulated with a standard 0.8-μm CMOS technology. The output voltage keeps 800mV, and its fractional temperature coefficient is 9.94 ppm/℃ over the temperature range from -100℃ to 150℃ at a zero-bias. The PSRR of the output voltage is -42.55dB at 100Hz. The minimum power-supply voltage is 2.1V. The output voltage can be shifted down to 670mV while maintaining its temperature-insensitivity.
- 社団法人電子情報通信学会の論文
- 2005-02-01
著者
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IKEDA Hidetoshi
Department of Neurosurgery,Tohoku University
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TAKAKUBO Hajime
Department of Electrical,Electronic, and Communication Engineering, Chuo University
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TAKAKUBO Kawori
Department of Electronics Engineering, Tokai University
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Ikeda H
Department Of Electrical Electronic And Communication Engineering Chuo University
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Takakubo K
Department Of Electronic & Communication Meiji University
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Takakubo Kawori
Department Of Electronics And Bioinformatics Meiji University
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Takakubo H
Department Of Electrical Electronic And Communication Engineering Chuo University
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Takakubo Hajime
Department Of Electrical Electronic And Communication Engineering
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Ikeda Hidetoshi
Department Of Neurosurgery Ohara Medical Center
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TAKAKUBO Kawori
Department of Electronic & Communication, Meiji University
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