A Low Voltage Tristate Buffer with Complementary BiCMOS Charge Pump(VLSI Design Technology and CAD)

概要

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A novel high speed, low voltage BiCMOS tristate buffer is presented and its performance characteristics are investigated by using PSPICE simulation. The results obtained are compared with a general CMOS and a couple of previous BiCMOS tristate buffer circuits which are conventional BiCMOS and complementary BiCMOS tristate buffer circuits. It is shown that the proposed BiCMOS tristate buffer circuit outperforms other previous tristate buffer circuits. At lower supply voltage, the proposed circuit has been shown more advantageous speed over previous circuits and it guarantees speed advantage over previous circuits even supply voltage application is at 1.5 volt. The pass transistor technique with a single MOS transistor driving is used to improve the driving capability. Furthermore, a complementary BiCMOS charge pump technique is used to eliminate the voltage loss due to base-emitter turn on voltage and to enhance the driving capability. With the positive and negative charge pump, it can be realized a high speed at low voltage with full swing operation without performance degradation due to shunt CMOS circuit as same as previous complementary BiCMOS tristate buffer circuit.
社団法人電子情報通信学会の論文
2004-07-01