FPGA Implementation of FIR Filter Using 2-Bit Parallel Distributed Arithmetic(Digital Signal Processing)

スポンサーリンク

概要

• 論文の詳細を見る

• An efficient architecture for a FPGA symmetry FIR filter is proposed that employs 2-bit parallel-distributed arithmetic (2-bit PDA). The partial product is pre-calculated and saved into the distributed ROM. This eliminates the large amount of logic needed to compute multiplication results. The proposed architecture consumes less area and offers higher speed operation because the multiplier is omitted.

• 社団法人電子情報通信学会の論文
• 2004-05-01

著者

• CHANG Shu-Ming

  Department of Electrical Engineering, National Sun Yat-sen University

• Chang Shu-ming

  Department Of Electrical Engineering National Dong Hwa University

• Jeng S‐s

  Department Of Electrical Engineering National Dong Hwa University

• JENG Shiann-Shiun

  Department of Electrical Engineering, National Dong Hwa University

• LAN Bor-Shuh

  Department of Electrical Engineering, National Dong Hwa University

• Lan Bor-shuh

  Department Of Electrical Engineering National Dong Hwa University

• Jeng Shiann-shiun

  Department Of Electrical Engineering National Dong Hwa University

関連論文

• Characterization of Thermally Annealed Fluorinated Silicon Dioxide Films Prepared by Liquid-Phase Deposition
• FPGA Implementation of FIR Filter Using 2-Bit Parallel Distributed Arithmetic(Digital Signal Processing)
• Multi-Mode Digital IF Downconverter for Software Radio Application(Software Defined Radio Technology and Its Applications)
• Performance Evaluation of Smart Antenna for Third-Generation W-CDMA Systems
• Laser Chaos Induced by Delayed-Feedback and External Modulation

スポンサーリンク