Coupling-Driven Data Bus Encoding for SoC Video Architectures(System Level Design)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper presents the definition and implementation design of a low power data bus encoding scheme dedicated to system on chip video architectures. Trends in CMOS technologies focus the attention on the energy consumption issue related to on-chip global communication; this is especially true for data dominated applications such as video processing. Taking into account scaling effects a novel coupling-aware bus power model is used to investigate the statistical properties of video data collected in the system bus of a reference hardware/software H.263/MPEG-4 video coder architecture. The results of this analysis and the low complexity requirements drive the definition of a bus encoding scheme called CDSPBI (Coupling Driven Separated Partial Bus Invert), optimized ad-hoc for video data. A VLSI implementation of the coding circuits completes the work with an area/delay/power characterization that shows the effectiveness of the proposed scheme in terms of global power saving for a small circuit area overhead.

• 社団法人電子情報通信学会の論文
• 2004-12-01

著者

• Fanucci Luca

  Ieiit National Research Council

• Locatelli Riccardo

  Dep. Of Inf. Engineering University Of Pisa Via Caruso

• MINGHI Andrea

  Dep. of Inf. Engineering, University of Pisa, Via Caruso

• Minghi Andrea

  Dep. Of Inf. Engineering University Of Pisa Via Caruso

関連論文

• Coupling-Driven Data Bus Encoding for SoC Video Architectures(System Level Design)(VLSI Design and CAD Algorithms)
• Low Complexity Detection for UTRA-TDD Receivers(Communication Theory and Systems)(Applications and Implementations of Digital Signal Processing)

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