An IP Synthesizer for Limited-Resource DWT Processor(System Level Design)(<Special Section>VLSI Design and CAD Algorithms)

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概要

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• This paper presents a VLSI design methodology for the MAC-level DWT/IDWT processor based on a novel limited-resource scheduling algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of limited-resource FIR filtering has been developed for the scheduling of the MAC-level DWT/IDWT signal processing. Given a set of architecture constraints and DWT parameters, the scheduling algorithmcan generate f our scheduling matrices that drive the data path to perform the DWT computation. Because the memory for the inter-octave is considered with the register of FIR filter, the memory size is less than the traditional architecture. Besides, based on the limited-resource scheduling algorithm, an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPs can be efficiently realized by tuning the parameters and applied for signal processing applications.

• 社団法人電子情報通信学会の論文
• 2004-12-01

著者

• Dung L‐r

  Department Of Electrical And Control Engineering National Chiao-tung University

• Dung Lan-rong

  Department Of Electrical And Control Engineering National Chiao-tung University

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