Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation(Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• As a design flow for low-power FPGA implementation, Datapath-Layout-Driven Design (DLDD) has been proposed. This letter reports the effect of DLDD for standard-cell-based ASIC implementation, and proposes necessary improvements. Experimental results shows that about 8.3% reduction of power dissipation is achieved in the best case.

• 社団法人電子情報通信学会の論文
• 2002-12-01

著者

• Ochi Hiroyuki

  Faculty Of Information Sciences Hiroshima City University

• Tsuda Takao

  Faculty Of Engineering Osaka University

• KAKIMOTO Takahiro

  Faculty of Information Sciences, Hiroshima City University

• Kakimoto T

  Faculty Of Information Sciences Hiroshima City University:(present Address)oki Electric Industry Co.

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• Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation(Special Section on VLSI Design and CAD Algorithms)
• 数値シミュレーション Multidimensional Uniformity of Pseudorandom and Quasirandom Sequences

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