Area-Efficient Multi-Port SRAMs for On-Chip Data-Storage with High Random-Access Bandwidth and Large Storage Capacity

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概要

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• The recent trend towards highly parallel on-chip data processing, as e. g. in single-chip processors with paralle execution capability of multiple instructions, leads to the requirement of on-chip data storage with high random-access bandwidth, parallel access capability and large capacity. The first two requirements call for the application of multi-ported memories. However, the conventional architecture, based on multi-port storage cells for earch bit, cannot efficiently realize the large storage capacity, because cell area explodes due to a quadratic increase with port number (N). A promising method for obtaining area efficiency is to increase the size of the smallest unit with N-port capability, e. g. by introducing N-port capability on the level of blocks of 1-port cells and not for each cell. We report a quantitative analysis of this method for the SRAM case, which is based on design data in a 0.5μm, 2-metal CMOS technology. Achievable area-reduction magnitudes in comparison to the conventional architecture are found to be enormous and to accelerate as a function of N. Reduction factors to areas<1/2, <1/5, <1/14and<1/30 are estimated for 4, 8, 16 and 32 ports, respectively. Since the demerit of the proposed approach is an increased access-rejection probability, a trade-off between area reduction and allowable access-rejection probability is always necessary for practical applications. This is discussed for the application of multiport cache memories.

• 社団法人電子情報通信学会の論文
• 2001-03-01

著者

• Mattausch H

  Hiroshima Univ. Higashi‐hiroshima‐shi Jpn

• Mattausch Hans

  The Research Center For Nanodevices And Systems Hiroshima University

• Kishi Koji

  The Research Center For Nanodevices And Systems Hiroshima University

• GYOHTEN Takayuki

  the Research Center for Nanodevices and Systems, Hiroshima University

• Gyohten T

  Hiroshima Univ. Higashi‐hiroshima Jpn

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