BIST Circuit Macro Using Microprogram ROM for LSI Memories

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概要

• 論文の詳細を見る

• We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and V_ltOHgt/V_ltOLgt differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.

• 社団法人電子情報通信学会の論文
• 1995-07-25

著者

• Takeshima Toshio

  Ulsi Device Development Laboratories Nec Corporation

• Koike H

  Microelectronics Research Laboratories Nec Corporation

• Takada Masahide

  Microelectronics Research Laboratories Nec Corporation

• Koike Hiroki

  Microelectronics Research Laboratories, NEC Corporation

関連論文

• Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
• BIST Circuit Macro Using Microprogram ROM for LSI Memories

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