Overview of Low-Power ULSI Circuit Techniques
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概要
- 論文の詳細を見る
This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSIs now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing : 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static circuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSl circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.
- 社団法人電子情報通信学会の論文
- 1995-04-25
著者
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Kuroda T
Keio Univ. Yokohama‐shi Jpn
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Kuroda Tadahiro
Toshiba Corporation, Semiconductor Device Engineering Lab.
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Sakurai Takayasu
Toshiba Corporation, Semiconductor Device Engineering Lab.
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Sakurai Takayasu
Toshiba Corporation Semiconductor Device Engineering Lab.
関連論文
- Variable Threshold-Voltage CMOS Technology (Special Issue on Low-power LSIs and Technologies)
- Overview of Low-Power ULSI Circuit Techniques