An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults

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概要

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• The authors previously proposed a reconfigurable architecture called the "XL-scheme" [10] in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model [5], [11]. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.

• 社団法人電子情報通信学会の論文
• 1997-09-25

著者

• Takanami Itsuo

  The Faculty Of Engineering Iwate University

• HORITA Tadayoshi

  the Faculty of Engineering, Iwate University

• Horita Tadayoshi

  The Faculty Of Engineering Iwate University

関連論文

• An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults
• An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults

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