Address Addition and Decoding without Carry Propagation

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概要

• 論文の詳細を見る

• The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.

• 社団法人電子情報通信学会の論文
• 1997-01-25

著者

• HWANG Seung

  Department of Biochemistry, Hanyang University & GenoCheck Co. Ltd.

• Hwang Seung

  Department Of Biochemistry And Molecular Biology Hanyang University & Genocheck Co. Ltd.

• Hwang S

  Department Of Electrical Engineering Korea Advanced Institute Of Science And Technology

• Lee Y‐h

  National Cheng Kung Univ. Tainan Twn

• LEE Yung-Hei

  Department of Electrical Engineering, Korea Advanced Institute of Science and Technology

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