Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design

概要

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We present an efficient heuristic algorithm to reduce glitch power dissipation in CMOS digital circuits. In this paper, gate sizing is classirfied into three types and the buffer insertion is classified into two types. The proposed algorithm combines three types of gate sizing and two types of buffer insertion into a single optimization process to maximize the glitch reduction. The efficiency of our algorithm has been verified on LGSynth91 benchmark circuits with a 0.5μm standard cell library. Experimental results show an average of 69.98% glitch reduction and 28.69% power reduction that are much better than those of gate sizing and buffer insertion performed independently.
社団法人電子情報通信学会の論文
2002-01-01