A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing

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概要

• 論文の詳細を見る

• This paper presents methods of combining buffer insertion and transistor sizing into a single post-layout optimization. The proposed method considers the tradeoff between upsizing transistors and inserting buffers then chooses the solution with the lowest possible power and area cost. The proposed method is efficient and tunable in that optimality can be traded for compute time.

• 社団法人電子情報通信学会の論文
• 2001-10-01

著者

• Kim Juho

  The Department Of Computer Science Sogang University

• LEE Sungkun

  SiliconCraft Inc.

関連論文

• Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design
• A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing

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