A Multimedia Architecture Extension for an Embedded RISC Processor

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概要

• 論文の詳細を見る

• This paper presents a multimedia architecture extension design for a 200-MHz, 1.6-GOPS embedded RISC processor. The datapath architecture of the processor which realizes parallel execution of data transfer and SIMD (single instruction stream multiple data stream) parallel arithmetic operations is designed. Four SIMD parallel 16-bit MAC (multiply-accumulation) instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 16-bit accumulation. This parallel 16-bit MAC on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as the correlation and the matrix-vector multiplications in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, a 2D-IDCT which satisfies the IEEE1180 can be implemented in 202 cycles.

• 2001-09-01

著者

• KURODA Ichiro

  Multimedia Research Laboratories, NEC Corporation

• Kuroda Ichiro

  Multimedia Research Laboratories Nec Corporation

• NADEHARA Kouhei

  Multimedia Research Laboratories, NEC Corporation

• Nadehara Kouhei

  Multimedia Research Laboratories Nec Corporation

• KURODA Ichiro

  Multimedia Information Research Laboratories, NEC Corporation

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