Register Constraint Analysis to Minimize Spill Code for Application Specific DSPs(Special Section on Papers Selected from ITC-CSCC 2000)

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概要

• 論文の詳細を見る

• This letter presents a method which attempts to minimize the number of spill codes to resolve usage conflicts of distributed registers in application specific DSPs. It searches for a set of ordering restrictions among operations which sequentialize the lifetimes of the values residing in the same register as much as possible. Experimental results show that the proposed analysis method reduces the number of register spills into 28%.

• 社団法人電子情報通信学会の論文
• 2001-06-01

著者

• Ishiura Nagisa

  The Graduate School Of Engineering Osaka University

• WATANABE Tatsuo

  the Graduate School of Engineering, Osaka University

• Watanabe Tatsuo

  The Graduate School Of Engineering Osaka University

関連論文

• Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes (Special Section on VLSI Design and CAD Algorithms)
• A Binding Algorithm for Retargetable Compilation to Non-orthogonal DSP Architectures (Special Section on VLSI Design and CAD Algorithms)
• Register Constraint Analysis to Minimize Spill Code for Application Specific DSPs(Special Section on Papers Selected from ITC-CSCC 2000)

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