Higher Order Delta-Sigma AD Converter with Optimized Stable Coefficients(Analog Signal Processing)(Regular Section)
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概要
- 論文の詳細を見る
Optimization procedure on higher order Delta-sigma(ΔΣ)modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method[3]. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR(Signal to Noise Ratio)degradation. The Optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm[5], and remains the stable input limit satisfies the orginal design requirement.
- 社団法人電子情報通信学会の論文
- 2001-03-01
著者
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HIRANO SATOSHI
Department of Surgical Oncology, Hokkaido University Graduate School of Medicine
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Hirano Satoshi
Frontier Research Program For Subduction Dynamics Japan Marine Science And Technology Center
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Hirano Satoshi
Department Of Electrical And Computer Engineering Nagoya Institute Of Technology
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ZHANG Yikui
Department of Electrical and Computer Engineering, Nagoya Institute of Technology
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HAYAHARA Etsuro
Department of Electrical and Computer Engineering, Nagoya Institute of Technology
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Zhang Y
Department Of Electrical And Computer Engineering Nagoya Institute Of Technology
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