Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time(Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number os gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.

• 社団法人電子情報通信学会の論文
• 2001-11-01

著者

• Yoshimura Masayoshi

  Second Department Of Internal Medicine Kansai Medical University

• Yoshimura Masayoshi

  Corporate Development Division Semiconductor Company Matsushita Electric Industrial Co. Ltd.

• HOSOKAWA Toshinori

  Corporate Development Division, Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

• OHTA Mitsuyasu

  Corporate Development Division, Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

• Ohta M

  Corporate Development Division Semiconductor Company Matsushita Electric Industrial Co. Ltd.

• Hosokawa Toshinori

  Corporate Development Division Semiconductor Company Matsushita Electric Industrial Co. Ltd.:design

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• Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops(Special Issue on Test and Diagnosis of VLSI)

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