Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
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概要
- 論文の詳細を見る
A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventional RT level manual design in HDL.
- 社団法人電子情報通信学会の論文
- 2000-03-25
著者
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TAKEUCHI Yoshinori
the Department of Informatics and Mathematical Science, Graduate School of Engineering Science, Osak
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Imai Masaharu
The Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka
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Shiomi Akichika
The Department Of Computer Science Shizuoka University
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Itoh Makiko
The Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka
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Takeuchi Yoshinori
The Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka
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Takeuchi Yoshinori
The Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka
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Imai Masaharu
The Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka
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