A Scalable Pipelined Memory Architecture for Fast ATM Packet Switching

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概要

• 論文の詳細を見る

• This paper describes the design of a scalable pipelined memory buffer for a shared scalable buffer ATM switch. The memory architecture provides high speed and scalability, and eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. The architecture consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of a designed scalable memory is 4 ns. The designed memory is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SHAM memory banks. It is integrated in 0.6 μm double-metal single-poly CMOS technology.

• 社団法人電子情報通信学会の論文
• 1999-09-25

著者

• Lee M

  Vlsi & Cad Lab. Department Of Electronic Engineering Yonsei University

• JEONG Gab

  Switching Technology Department, ETRI

• LEE Moon

  VLSI & CAD Lab., Department of Electronic Engineering, Yonsei University

• Jeong Gab

  Switching Technology Department Etri

関連論文

• A Scalable Pipelined Memory Architecture for Fast ATM Packet Switching
• Throughput Enhancement of Shared Multi-buffer ATM Switch in Multicast Environments
• Jitter Reduction in CBR MPEG-2 Transport Stream Packet Communications over Lossy ATM Network

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