IC Implementation of Current-Mode Chaotic Neuron Circuit

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概要

• 論文の詳細を見る

• This paper describes an IC implementation of current-mode chaotic neuron circuit for the chaotic neural network. The chaotic neuron circuit which composes of a first generation switched-current integrator and a conventional current amplifier is fabricated in a standard 0.8 μm CMOS technology. Experimental results of the chaotic neuron circuit reproduce the dynamical behavior of the chaotic neuron model.

• 社団法人電子情報通信学会の論文
• 1999-11-25

著者

• Kanou Nobuo

  Faculty of Engineering, Tokyo Denki University

• Kanou Nobuo

  Faculty Of Engineering Tokyo Denki University

関連論文

• A Current-Mode Implementation of a Chaotic Neuron Model Using a SI Integrator
• A Current-Mode Circuit of a Chaotic Neuron Model
• IC Implementation of Current-Mode Chaotic Neuron Circuit

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