The Impact of nm CMOS Technology on Wireless Circuit and System (Devices:先端デバイスの基礎と応用に関するアジアワークショップ)

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The impact of CMOS technology scaling on the various RF circuit components such as active, passive and digital circuits are presented. For the active circuits, the impact of scaling on the LNA noise and linearity is thoroughly analyzed first. Then two new circuits inventions named CCPP (CMOS Complementary Parallel Push-pull) circuit and the use of parasitic V-NPN (Vertical-NPN) bipolar transistor for DCR (Direct Conversion Receiver) are introduced. In CCPP, the high RF performance of PMOS comparable to NMOS, provides single ended differential RF signal processing capability without the use of bulky balun. The use of parasitic V-NPN (Vertical-NPN) bipolar transistor, available free in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and DC offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive devices, performance scaling for the inductor, variable capacitors, MIM capacitor, and switched capacitor, are discussed. Both the forward scaling of the active layer as well as the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Because of the accuracy, adaptability, flexibility, and programmability, digital circuitries are employed more and more in RF front end these days. In this last part of this paper, the impact of CMOS scaling on the various digital circuits are analyzed, taking the digital modem blocks, on the various digital calibration circuits, on the switching RF power amplifier, and finally on the software defined radio, as examples.
社団法人電子情報通信学会の論文
2003-06-24

The Impact of nm CMOS Technology on Wireless Circuit and System (Devices:先端デバイスの基礎と応用に関するアジアワークショップ)

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