Implementation of FIFO Buffer Using Cache Memory (デザインガイア2002--VLSI設計の新しい大地を考える研究会 テーマ:チップマルチプロセッサおよび一般)
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概要
- 論文の詳細を見る
Conventional caches are not always made use of in some familiar applications because of no locality in memory accesses. To make use of a large cache memory space in a today's processor, We propose a built-in FIFO buffer based on a concept of reconfigurable caches where cache memory space is divided into several partitions dynamically. The FIFO mechanism can be implemented with small additional hardware, avoid memory fragmentation, and improve performance of data accesses.
- 一般社団法人情報処理学会の論文
- 2002-11-27
著者
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Tanaka Kiyofumi
School Of Information Science Japan Advanced Institute Of Science And Technology:"information A
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KHALID KHAIRUDDIN
School of Information Science, Japan Advanced Institute of Science and Technology
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Khalid Khairuddin
School Of Information Science Japan Advanced Institute Of Science And Technology
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田中 清史
School of Information Science, Japan Advanced Institute of Science and Technology
関連論文
- Implementation of FIFO Buffer Using Cache Memory (デザインガイア2002--VLSI設計の新しい大地を考える研究会 テーマ:チップマルチプロセッサおよび一般)
- Evaluation of Cache Memory as FIFO Buffer (「ハイパフォーマンスコンピューティングとアーキテクチャの評価」に関する北海道ワークショップ(HOKKE-2003))