A 64-bit RISC Microprocessor for Parallel Computer Systems

概要

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This paper describes a microprocessor designed for a (Processing Element) PE of a scientific parallel computer system. This processor consists of three operational units: an instruction fetch and decode unit, an integer/address operation unit, and a floating-point operation unit. The chip is fabricated by means of a two-AI-layer, 1.2 /μm N-well CMOS technology, and contains 440 K transistors in a 14.4 x 13.5 mm^2 die. The processor, which employs RlSC architecture and Harvard-style bus organization, executes most of its 47 instructions, including 64-bit floating-point operations, in one 50-nsec cycle (20 MFLOPS/20 MIPS) with a 5-stage pipeline organization. The performance of the processor and its special functions for parallel computer systems are also discussed.
一般社団法人情報処理学会の論文
1990-08-25