Processor Architecture and Evaluation which Correspond to Deviation of Memory Latency

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概要

• 論文の詳細を見る

• The deviation of the memory latency is hard to predict for software especially on the SMP or NUMA systems. As the correspondence method by hardware, the multi-thread processor has been devised. However, it is not general to improve a performance in a single program. We have been proposed SCALT which has a buffer as a software context. For the deviation of a latency problem, a instruction which checks existence of the data arrival to a buffer has been proposed. This report describes the SCALT and evaluation results the performance of SCALT with buffer check instruction with an event-driven simulator for SMP system.

• 東海大学の論文

著者

• Shimizu Naohiko

  Department Of Communication Engineering

• MITAKE Daisuke

  Course of Electrical Engineering

関連論文

• Processor Architecture and Evaluation which Correspond to Deviation of Memory Latency
• Parallel Pipelining SOR Method for an Iterative Linear Equation Solver on a Distributed Memory Parallel Processor
• Design of A Memory Latency Tolerant Processor (SCALT)

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