Design of A Memory Latency Tolerant Processor (SCALT)

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概要

• 論文の詳細を見る

• In this paper, we introduce a design of a memory latency tolerant processor called SCALT. We present that adding the latency tolerant features on the conventional load/store architecture processor will not bring complexity to the design and the critical path of the processor will not be affected with those features. We also present the logic synthesis result of our processor. It shows that our processor will be able to fabricate with the 0.8μm process. Of course smaller feature size process will also fit to our design.

• 東海大学の論文

著者

• Shimizu Naohiko

  Department Of Communications Engineering

• Shimizu Naohiko

  Department Of Communication Engineering

• MITAKE Daisuke

  Course of Electrical Engineering

関連論文

• Processor Architecture and Evaluation which Correspond to Deviation of Memory Latency
• Parallel Pipelining SOR Method for an Iterative Linear Equation Solver on a Distributed Memory Parallel Processor
• Design of A Memory Latency Tolerant Processor (SCALT)

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