A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation

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概要

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• We fabricated a 2: 1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120Gbit/s with a power dissipation of 1.27W and output amplitude of 520mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4W.

• （社）電子情報通信学会の論文
• 2010-08-01

著者

• Takagi Akio

  Anritsu Devices

• Matsuoka Yutaka

  Anritsu Devices

• ARAYASHIKI Yutaka

  Anritsu Devices

• OHKUBO Yukio

  Anritsu Devices

• MATSUMOTO Taisuke

  Anritsu Devices

• AMANO Yoshiaki

  Anritsu Devices

関連論文

• A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation
• High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors

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