Adopting the Drowsy Technique for Instruction Caches : A Soft Error Perspective
スポンサーリンク
概要
- 論文の詳細を見る
As technology scales down, leakage energy accounts for a greater proportion of total energy. Applying the drowsy technique to a cache, is regarded as one of the most efficient techniques for reducing leakage energy. However, it increases the Soft Error Rate (SER), thus, many researchers doubt the reliability of the drowsy technique. In this paper, we show several reasons why the instruction cache can adopt the drowsy technique without reliability problems. First, an instruction cache always stores read-only data, leading to soft error recovery by re-fetching the instructions from lower level memory. Second, the effect of the re-fetching caused by soft errors on performance is negligible. Additionally, a considerable percentage of soft errors can occur without harming the performance. Lastly, unrecoverable soft errors can be controlled by the scrubbing method. The simulation results show that the drowsy instruction cache rarely increases the rate of unrecoverable errors and negligibly degrades the performance.
- (社)電子情報通信学会の論文
- 2008-07-01
著者
-
Jhon Chu
School Of Computer Science And Engineering Seoul National University
-
SHIN Soong
School of Computer Science and Engineering, Seoul National University
-
CHUNG Sung
School of Computer and Information Technology, Korea University
-
CHUNG Eui-Young
School of Electrical and Electronic Engineering, Yonsei University
-
Chung Sung
School Of Computer And Information Technology Korea University
-
Shin Soong
School Of Computer Science And Engineering Seoul National University
-
Chung Eui-young
School Of Electrical And Electronic Engineering Yonsei University
関連論文
- Adopting the Drowsy Technique for Instruction Caches : A Soft Error Perspective
- 516 A Study on Fabrication of PDP Barrier Ribs Using Micro Tooling Process
- Analytical memory bandwidth model for many-core processor based systems
- Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors
- Power Failure Protection Scheme for Reliable High-Performance Solid State Disks
- Page overwriting method for performance improvement of NAND flash memories