A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator

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概要

• 論文の詳細を見る

• We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-μm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.

• （社）電子情報通信学会の論文
• 2008-05-01

著者

• Choi Woo‐young

  Yonsei Univ. Seoul Kor

• CHOI Woo-Young

  Yonsei University

• SEONG Chang-Kyung

  Yonsei University

• LEE Seung-Woo

  Electronics and Telecommunications Research Institute

• Lee Seung‐woo

  Electronics And Telecommunications Research Institute

関連論文

• Linear Analysis of Feedforward Ring Oscillators
• A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator
• A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution(Electronic Circuits)
• Linear Analysis of Feedforward Ring Oscillators

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