A Design of the Signal Processing Hardware Platform for Communication Systems
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概要
- 論文の詳細を見る
In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900K gates, two DSPs with maximum 8,000 MIPS at 1GHz clock, 2-channel ADC and DAC supporting maximum 125MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.
- （社）電子情報通信学会の論文
- 2008-03-01
著者
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LEE Byung
Department of Bioengineering, Faculty of Engineering, Soka University
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Cho Sung
Hanyang Univ. Seoul Kor
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CHO Sung
College of Information and Communications, Hanyang University
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Cho Sung
College Of Information & Communications Hanyang University
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Lee Byung
Department Of Anatomy Seoul National University College Of Medicine
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Lee Byung
Department Of Electronics And Computer Engineering Hanyang University
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