A Methodology for the Design of MOS Current-Mode Logic Circuits

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概要

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• In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130nm CMOS process.

• 2010-02-01

著者

• CARUSO Giuseppe

  Dipartimento di Ingegneria Elettrica, Elettronica e delle Telecomunicazioni, Università di Palermo

• Caruso Giuseppe

  Dipartimento Di Ingegneria Elettrica Elettronica E Delle Telecomunicazioni Universita Di Palermo

• Macchiarella Alessio

  Dipartimento Di Fisica Della Materia E Ingegneria Elettronica Universita Di Messina

• Caruso Giuseppe

  Dipartimento di Energia, Ingegneria dellInformazione e Modelli Matematici, Università di Palermo

関連論文

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• A Methodology for the Design of MOS Current-Mode Logic Circuits
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• A Heuristic Algorithm for Boolean Factoring
• A delay model valid in all the regions of operation of the MOS transistor for the energy-efficient design of MCML gates

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