Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter

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概要

• 論文の詳細を見る

• This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225mW at the sampling speed of 250Msample/s and the power supply of 3.3V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.

• （社）電子情報通信学会の論文
• 2009-08-01

著者

• Jin Yong-gao

  Yanbian University

• Choi Ho-yong

  Chungbuk National University

• Kim Nam‐soo

  Chungbuk National University

• CUI Zhi-Yuan

  Chungbuk National University

• KIM Nam-Soo

  Chungbuk National University

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