A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique
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概要
- 論文の詳細を見る
- 2009-05-01
著者
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CHAN Pak
School of Electrical and Electronic Engineering, Nanyang Technological University
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Chan Pak
School Of Electrical And Electronic Engineering Nanyang Technological University
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FAN Xian
School of Electrical and Electronic Engineering, Nanyang Technological University
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CHEE Piew
Institute for Infocomm Research
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Fan Xian
School Of Electrical And Electronic Engineering Nanyang Technological University
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Chan Pak
Nanyang Technological Univ. Singapore
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Chan Pak
School Of Electrical And Electronic Engineering Nanyang Technological Univ.
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CHAN Pak
School of Electrical & Electronic Engineering, Nanyang Technological University
関連論文
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- A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique
- Design of High-Performance Analog Circuits Using Wideband g_m-Enhanced MOS Composite Transistors
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