Redundant Vias Insertion for Performance Enhancement in 3D ICs
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概要
- 論文の詳細を見る
Three dimensional (3D) integrated circuits (ICs) have the potential to significantly enhance VLSI chip performance, functionality and device packing density. Interconnects delay and signal integrity issues are critical in chip design. In this paper, we extend the idea of redundant via insertion of conventional 2D ICs and propose an approach for vias insertion/placement in 3D ICs to minimize the propagation delay of interconnects with the consideration of signal integrity. The simulation results based on a 65nm CMOS technology demonstrate that our approach in general can result in a 9% improvement in average delay and a 26% decrease in reflection coefficient. It is also shown that the proposed approach can be more effective for interconnects delay improvement when it is integrated with the buffer insertion in 3D ICs.
- （社）電子情報通信学会の論文
- 2008-04-01
著者
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Jiang Xiaohong
Graduate School of Information Sciences, Tohoku University
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HORIGUCHI Susumu
Graduate School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)
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Jiang X
Graduate School Of Information Sciences Jaist:(present Address)graduate School Of Information Scienc
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Jiang Xiaohong
Tohoku Univ.
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Jiang Xiaohong
The Graduate School Of Information Sciences Tohoku University
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Jiang Xiaohong
Graduate School Of Information Science Japan Advanced Institute Of Science And Technology Jaist
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Zhang Xu
Graduate School Of Information Science Tohoku University
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Horiguchi Susumu
Tohoku Univ. Sendai‐shi Jpn
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Susumu Horiguchi
Graduate School Of Information Science Tohoku University
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Horiguchi Susumu
Graduate School Of Information Science Jaist
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Horiguchi Susumu
Graduate School Of Computer Science Japan Advanced Institute Of Science And Technology
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Xu Zhang
Graduate School of Information Science, Tohoku University
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