6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator

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概要

• 論文の詳細を見る

• In this paper, we describe a 6-bit 1.6-GS/s flash analog to digital converter (ADC). To reduce the power consumption and active area, we propose a new interpolation architecture using a symmetric three-input comparator. This ADC achieves 5.56 effective bits for input frequencies up to 220MHz at 1.6GS/s, and almost five effective bits for 660MHz input at 1.6GS/s. Peak INL and DNL are less than 0.5LSB and 0.45LSB, respectively. This ADC consumes 85mW from 1.8V at 1.6GS/s and occupies an active area of 0.27mm2. It is fabricated in 0.18-μm CMOS.

• （社）電子情報通信学会の論文
• 2008-03-01

著者

• KIM Suki

  Korea University

• Kim Yun-jeong

  Korea University

• LEE Jong-Ho

  Korea University

• KOO Ja-Hyun

  Korea University

• BAEK Kwang-Hyun

  Chung-Ang University

• Kim Suki

  Korea Univ. Seoul Kor

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