Digitally Controlled Duty Cycle Corrector with 1ps Resolution(Electronic Circuits)

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概要

• 論文の詳細を見る

• This letter describes a digitally controlled duty cycle corrector (DCC) with 1ps resolution. A new half period delay line (HPDL) control scheme using a delay locked loop (DLL) is proposed. The DCC has an output duty error less than 0.5% for 25% input duty error and operates correctly from 200MHz to 800MHz in a 0.18μm CMOS technology.

• 社団法人電子情報通信学会の論文
• 2007-09-01

著者

• KIM Suki

  Korea University

• BAEK Kwang-Hyun

  Chung-Ang University

• Baek Kwang‐hyun

  Chung‐ang Univ. Seoul Kor

• Kim Suki

  Korea Univ. Seoul Kor

• JO Youngkwon

  Korea University

• PARK Hoyoung

  Korea University

• YANG Sanghyuk

  Korea University

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• Digitally Controlled Duty Cycle Corrector with 1ps Resolution(Electronic Circuits)
• A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform

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