Low-Power Switched Current Memory Cell with CMOS-Type Configuration

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概要

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• This letter presents a low-power switched current (SI) memory cell with CMOS-type configuration. By combining nMOS and pMOS in the SI memory cell and using a polarity discrimination circuit, we design a CMOS-type SI memory cell which eliminates the quiescent current in the SI memory cell. The simulation result shows that the CMOS-type SI memory cell consumes less power than the conventional class-AB memory cell.

• （社）電子情報通信学会の論文
• 2008-01-01

著者

• Arai Eisuke

  Graduate School Of Engineering Nagoya Institute Of Technology

• Terada Nobuyuki

  Graduate School Of Engineering Nagoya Institute Of Technology

• KATO Masashi

  Graduate School of Bioagricultural Sciences, Nagoya University

• OHATA Hirofumi

  Graduate School of Engineering, Nagoya Institute of Technology

• Ohata Hirofumi

  Graduate School Of Engineering Nagoya Institute Of Technology

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• Low-Power Switched Current Memory Cell with CMOS-Type Configuration

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