Ramp Voltage Testing for Detecting Interconnect Open Faults

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概要

• 論文の詳細を見る

• A method for detecting interconnect open faults of CMOS combinational circuits by applying a ramp voltage to the power supply terminal is proposed. The method can assign a known logic value to a fault location automatically by applying a ramp voltage and as a result, it requires only one test vector to detect a fault as a delay fault or an erroneous logic value at primary outputs. In this paper, we show fault detectability and effectiveness of the proposed method by simulation-based and theoretical analysis. We also expose that the method can be applicable to every fault location in a circuit and open faults with any value. Finally, we show ATPG results that are suitable to the proposed method.

• 2008-03-01

著者

• Miura Yukiya

  Faculty Of System Design Tokyo Metropolitan University

関連論文

• A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs
• Ramp Voltage Testing for Detecting Interconnect Open Faults

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