A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs

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概要

• 論文の詳細を見る

• Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (I_ltDDgt) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock frequency. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured I_ltDDgt is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.

• 社団法人電子情報通信学会の論文
• 1995-07-25

著者

• Miura Y

  Tokyo Metropolitan Univ. Hachioji‐shi Jpn

• Miura Yukiya

  Faculty Of System Design Tokyo Metropolitan University

• Naito Sachio

  Faculty of Engineering, Tokyo Metropolitan University

• Naito S

  Ntt Corp. Musashino‐shi Jpn

• Naito Sachio

  Faculty Of Engineering Tokyo Metropolitan University

• Miura Yukiya

  Faculty of Engineering, Tokyo Metropolitan University

関連論文

• A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs
• Ramp Voltage Testing for Detecting Interconnect Open Faults
• A Reconfigurable Parallel Processor Based on a TDLCA Model (Special Issue on Responsive Computer Systems)

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