(Bi,La)_4Ti_3O_<12> as a ferroelectric layer and SrTa_2O_6 as a buffer layer for metal-ferroelectric-metal-insulator-semiconductor field-effect transistor

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概要

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• The metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) using the (Bi,La)4Ti3O12 (BLT) as a ferroelectric and SrTa2O6 (STA) as a buffer layer is prepared. The Au/STA/Si structure shows about 1 nF/cm2 of the accumulation capacitance value which is equivalent to about 6.2 nm of SiO2. The leakage current density is lower than 107 A/cm2 under 5 V. The remanent polarization of the 420 nm-thick BLT film was 35.2 μC/cm2 at 450 kV/cm. The MFMIS-FET was fabricated with different area ratio (AI/AF) from 1 to 8. From the drain current-gate voltage characteristics at the drain voltage of 0.2 V, the memory window is only 0.5 V for the device with AI/AF = 1 but it is increased to 1.8 V as the AI/AF is increased to 8. For the AI/AF ratio of 8, the "on" state of the drain current of 1.12 × 10-5 A rapidly drops after 105 s to 2 × 10-6 A and the "off" state current increase from 10-7 A to 10-6 A after 105 s. The on/off current ratio decrease from 3 × 102 to 8.

• 公益社団法人 日本セラミックス協会の論文
• 2009-09-01

著者

• Kim Joo-nam

  School Of Electrical And Computer Engineering University Of Seoul

• Choi Yun-soo

  Department Of Geo-informatics University Of Seoul

• Park Byung-eun

  School Of Electrical And Computer Engineering University Of Seoul

• Park Byung-eun

  Dep. Of Electrical And Computer Engineering Univ. Of Seoul

関連論文

• Electrical properties of metal-ferroelectric-insulator-semiconductor field effect transistors (MFIS-FETs) using the polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE))/ZrO2/Si structure
• (Bi,La)_4Ti_3O_ as a ferroelectric layer and SrTa_2O_6 as a buffer layer for metal-ferroelectric-metal-insulator-semiconductor field-effect transistor
• Characteristics of Au/SBT/LZO/Si MFIS structure for ferroelectric-gate field-effect transistors

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