Device Design Considerations for Sub-50nm CMOS

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概要

• 論文の詳細を見る
• 1999-09-20

著者

• King Tsu-jae

  Department Of Electrical Engineering And Computer Sciences University Of California

• King Tsu-jae

  Department Of Electrical Engineering & Computer Sciences University Of California

関連論文

• Impact of Gate Microstructure on Complementary Metal-Oxide-Semiconductor Transistor Performance
• Device Design Considerations for Sub-50nm CMOS
• Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs

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