Drain Disturb Relaxation by Substrate bias Selecting Scheme for Sector Erase Flash Memory with Conventional Single Stacked Gate Cell Structure
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概要
- 論文の詳細を見る
- 1997-09-16
著者
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Shinmura N.
Vlsi Development Laboratories Ic Tenri Group Sharp Corporation
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YOSHIMI M.
VLSI Development Laboratories, IC Tenri Group, SHARP Corporation
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TANIGAMI T.
VLSI Development Laboratories, IC Tenri Group, SHARP Corporation
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HAKOZAKI K.
VLSI Development Laboratories, IC Tenri Group, SHARP Corporation
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SATO S.
VLSI Development Laboratories, IC Tenri Group, SHARP Corporation
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IGUCHI K.
VLSI Development Laboratories, IC Tenri Group, SHARP Corporation
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Tanigami T.
Vlsi Development Laboratories Ic Tenri Group Sharp Corporation
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Hakozaki K.
Vlsi Development Laboratories Ic Tenri Group Sharp Corporation
関連論文
- Drain Disturb Relaxation by Substrate bias Selecting Scheme for Sector Erase Flash Memory with Conventional Single Stacked Gate Cell Structure
- A Flash Memory Technology for Operating Voltage Reduction and Self-Convergence of the Over Erased Cells