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Kobe Univ. Kobe‐shi Jpn | 論文
- A Sub-100mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
- A 168-mW 2.4×-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI
- Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
- Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
- Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
- Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell
- A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells
- A Sub-100mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
- A 168-mW 2.4×-Real-Time 60-k Word Continuous Speech Recognition Processor VLSI