スポンサーリンク
Faculty of Engineering, The Univ. of Tokushima | 論文
- Genetic State Reduction Method of Incompletely Specified Machines(Graphs and Networks)
- Heuristic State Reduction Methods of Incompletely Specified Machines Preceding to Satisfy Covering Condition(Special Section of Papers Selected from ITC-CSCC'97)
- IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates(Special Issue on Test and Verification of VLSI)
- Lead Open Detection Based on Supply Current of CMOS LSIs(Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC 2003))
- CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply(Special Issue on Test and Verification of VLSI)
- Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits(Fault Detection)(Test and Verification of VLSI)
- Test Sequence Generation for Test Time Reduction of IDDQ Testing(Test Generation and Compaction)(Test and Verification of VLSI)
- Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field(Test)(Dependable Computing)
- Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States(Special Issue on Test and Verification of VLSI)
- Testable Static CMOS PLA for IDDQ Testing(Special Section on Papers Selected from ITC-CSCC 2000)