スポンサーリンク
Faculty Of Engineering Kyoto Sangyo University | 論文
- An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System (Special Issue on VLSI Testing and Testable Design)
- Temporal Verification of Real-Time Systems
- Towards Verification of Bit-Slice Circuits : Time-Space Modal Model Checking Approach
- Symbolic Model Checking of Deadlock Free Property of Task Control Architecture(Special Issue on Test and Verification of VLSI)
- Developments in prediction theories of the effective size of populations under selection
- Relaxation and luminescence processes in photo-excited phosphorescent Pt^ -compound N^N^C-Pt(Cl)
- A Proposal of a Mobile Radio Channel Database and Its Application to a Simple Channel Simulator (Special Issue on Personal, Indoor and Mobile Radio Communications)
- Prediction of Response and Inbreeding under Selection Based on Best Linear Unbiased Prediction in Closed Broiler Lines